To accommodate higher packing density in present integrated circuits, electrical connections to integrated circuit devices formed in a semiconductor substrate are made by multilayer interconnects. Each level of multilayer interconnects is supported over the semiconductor substrate by an interlevel dielectric. Generally, the integrated circuit structure includes a dielectric layer and metal lines are laid down in parallel strips on top of the dielectric layer. Additional levels of multilayer interconnects are formed over this dielectric layer, each including additional metal interconnects and an interlevel dielectric layer.
Fluoro-silicate glass (FSG) is one such material used as an inter-metal dielectric in semiconductor backend processing. FSG is used for many reasons, however, it is particularly well suited as a result of its improved gapfill capacity and reduced oxide dielectric constant. Lowering the dielectric constant reduces the inter/intra level capacitance of the metal lines, enhancing the operating speed of the devices.
FSG is often capped with a silicon-rich oxide (SRO) layer. The SRO layer attempts to reduce, if not prevent, fluorine from diffusing from the FSG layer to the bottom Ti/TiN metal stack. The SRO is typically deposited using a plasma enhanced chemical vapor deposition (PECVD) process. Often, however, this PECVD process causes the SRO layer to have various degrees of stress, depending on the deposition conditions. Therefore, the stress of the SRO layer can be tailored to go from slightly tensile, to highly compressive, depending on these conditions.
The most prevalent deposition condition that controls this degree of stress is the frequency at which the SRO layer is deposited. For example, the SRO layer may be deposited using a single or dual frequency process. As compared to a single frequency process, a dual frequency process requires that both the upper and lower electrodes be modulated at a particular, and often different, frequency.
The conventional practice is to deposit a single layer of slightly tensile SRO on top of the FSG layer using the single frequency process. Unfortunately, the tensile stress of the aluminum dominates the total stress, and the wafer becomes increasingly warped as the metal/dielectric levels are formed. A way to minimize this wafer warpage is to deposit a highly compressive SRO layer to counteract the tensile stress of the aluminum layer. This highly compressive SRO layer is typically formed using the aforementioned dual frequency process. Nevertheless, the highly compressive SRO layer often causes excessive lateral diffusion of fluorine to occur, which may further lead to metal attack.
Accordingly, what is needed in the art is a capping layer, or method of manufacture therefore, that does not introduce the problems introduced by the prior art capping layers.